The popularity of the SPICE circuit simulator has translated into various offerings, suited for different compute platforms. SPICE3, the latest Berkeley offering. It has the advantage of being freely available, to support a wide variety of models, and to run on all UNIX platforms. It is downloadable.HSPICE (from Avant!) offers a more robust, commercial version of SPICE. No free copies here. If interested, contact Avant!. PSPICE. This popular version of SPICE, available from Orcad (now Cadence) runs under the PC and Macintosh platforms. An evaluation version, which can handle small circuits with up to 10 transistors, is freely available. For a full fledged version or for more information, please contact Orcad. AIM-spice is a pc-version of SPICE with a revised user interface, simulation control, and with extra models. A student version can be downloaded. A complete list of all SPICE offerings (and software downloads for a wide range of platforms). MAGIC MAGIC is an interactive layout editor supporting on-line design rule checking and circuit extraction. It was developed by the group of John Ousterhout at the University of California at Berkeley. Click here to obtain a postscript version of the MAGIC tutorials (513851 Byte - tar format - compressed). Magic is downloadable. Versions for a variety of platforms can also be downloaded from the Digital Equipment Corporation MAGIC home page . You can also download the flea program (used in the software labs for the printing of the layouts). Observe that the latter has only been ported to the SUN platform. Another plot program, called MagicPlot is available from Yale A newer, more modern version of MAGIC is available from a company called MicroMagic.Check their Web-page for up-to-date information on their layout program, called MAX,which runs under SUN Solaris and LINUX.
TINA is a product of DesignSoft exclusively for Texas Instruments. This complimentary version is fully functional but does not support some other features available with the full version of TINA.For a complete list of available TINA-TI models, see: SpiceRack -- A Complete List Need HSpice models to aid in your design? Our HSpice model collection can be found here.
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This paper describes the design, implementation, and testing of a multichannel read-out and level 2 buffering circuit for a time measurement chip, L2I. L2I version 1.0 interfaces a four-channel version of the Time Measurement Cell (TMC) with the next level in the front-end electronics chain, the Data Collection Chip (DCC) for read-out of the SDC straw tracking detector. The chip was implemented as a standard cell design, except for a full-custom SRAM block, and fabricated in a 1.2 /ira n-well CMOS process. The total area of the chip including pads and off-chip driving circuitry is 12 ram2. Power consumption during full-speed operation is 12 mW. High level simulation of the circuitry was performed using Verilog HDL, and detailed timing simulations were carried out with Hspice. The chip was tested on an HP82000 IC test-station and was found functional with a minor design error in the control path. 2ff7e9595c
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